• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
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    • 专利摘要:
    1429850 Virtual addressing INTERNATIONAL BUSINESS MACHINES CORP 15 June 1973 [21 July 1972] 28630/73 Heading G4A Virtual addresses provided by a processor 1 (Fig. 1) for accessing a main store 6 are compared in comparator 2 with data representing the boundary in main store defining an area dedicated to storing selected programme information, e.g. the supervisor, within which virtual to real translation is not necessary, the virtual address being used to address the store when it falls within that area. As described, virtual addresses from register 4 are fed if comparison occurs via AND gate 13 to register 14 to address the store. Each virtual address is also fed to associative store 3 to cause read out of the corresponding real address, if it is stored therein, via gate 15 (inhibited when comparator 2 gives an output on lead 10) to the address register 14. If neither the comparator 2 nor the associative store 3 gives a match signal, gate 16 signals processor 1 to feed the virtual address to access segment and page tables stored in the main store and if found the real and virtual addresses are then placed in the associative store under the control of a least recently used logic circuit 20. If the page is not in the main store it is brought from, for example, disc storage and written in the main store in place of a selected page.
    公开号:SU784814A3
    申请号:SU731947680
    申请日:1973-06-20
    公开日:1980-11-30
    发明作者:Джон Келли Уоррен；Эдвард Ларсон Лоренс
    申请人:Интернэшнл Бизнес Машинз Корпорейшн (Инофирма)；
    IPC主号:
    专利说明:

    The invention relates to the field of storage devices.
    A device for selecting an address is known, which contains an associative memory block, an address memory block, 3 memory blocks on magnetic disks, in which address translation is used to address the address memory block flj. . θ
    The disadvantage of this device is the low speed.
    The closest technical solution to this invention is a device for selecting an address, containing registers, blocks of address and associative memory, logical elements [2].
    In this device, each virtual address is converted into a real 20 (absolute) address of the address memory block, i.e. virtual addresses are not used to directly address an address memory block. This leads to a decrease in the performance of 25 devices.
    The aim of the invention is to improve the performance of the device.
    This goal is achieved by the fact that in the device for selecting the address, 39 containing a random access memory block, one of the inputs of which is connected to the output of the first address register, the second address register, the output of which is connected to the input of the associative memory block, the first, a group of logical elements, one from the inputs of which are connected to the first output of the associative memory block, and the outputs - to the input of the logical block connected to the second address register and to the RAM block, the second and third groups of logical elements are introduced entom, information register and comparison circuit, the inputs of which are connected to the outputs of the second address register and information register, and the outputs are connected to one of the inputs of the logic elements of the second and third groups, the outputs of which are connected to the input of the first address register, other inputs of the logic elements are connected respectively to the outputs of the comparison circuit, the second address register and the second output of the associative memory block.
    In FIG. 1 shows a structural diagram of the proposed device; FIG. 2 is a graphical illustration of a process for addressing and paging, “FIG. 3 illustrates an alternative method dlya'ustanov '''I lonyya value: which may be entered into the boundary register.' -
    A device for selecting an address (see Fig. 1) contains a logical unit 1, which serves to process data; RAM block 2, memory block on magnetic disks 3, the first address register 4, used to store a real address and having an output 5, associative memory block 6. RAM block 2 contains zones' 7, 8, called the table of segments (7) and page tables (8-1 - 8-N).
    The device also contains the first 9, second 10 and third 11 groups of logical elements, an address setting unit 12, a comparison circuit 13, an information register 14, a second address register 15 used to store a virtual address. The RAM unit 2 also contains a nuclear zone 16. The inputs '17 and 18 of the comparison circuit 13 are connected to the outputs of the second address register 15 and the information register 14, and one of the outputs to one of the inputs of the logic elements 10 and 11. One of the inputs of the logic elements 9 connected to the first output 19 of block 6. Other inputs of the logic elements 9-11 are connected respectively to the other output of the comparison circuit 13, the output of the second address register 15 and the second output of the block 6. The outputs_ of the logical elements 10 and 11 are connected to the input of the first address register 4.
    The device operates as follows.
    When you want to select a cell from block 2 (see figure 1), then block 1 passes the virtual address to the comparison circuit 13 and block 6 through the -register 15.
    Register 14 stores a value equal to the 'high order bits (page size) of the boundary address in block 2, below' which virtual and corresponding real addresses are equal to them .... For example, if a page is two thousand bits, then the bottom twelve bits of the page address are not stored in register 14. Segment table 7 and page tables 8-1 to 8-N are in block 2. Table 7 has an input for each of N segments virtual memory in block 3. Each input has a 'hell'''r'esyyyuKaz'at e Pi 'beginning' of the corresponding page of the table from 8-1 to 8th. Each page table has many inputs for the pages of the corresponding segment, which can be called into block 2, the last input of the actual table contains the beginning of the page in the block '' ...... Signal 'by comparing with the elements of block 3. Each page pointer 2;
    from one of the outputs of the circuit, a logical I ’(* i '; is gated in order to let the virtual address into register 4, when the higher bits of the virtual address supplied from block 1 are less than the value stored in the register
    14. The same signal also comes as a prohibitory signal to the logic elements 11 in order to prevent the transfer of any real address from block 6 to register 4 when conversion is not required.
    The signals from the logic elements 9 are necessary in order to search for tables 7 and from 8-1 to 8-N, when the signals are applied to the inputs of these elements. The signals are fed to the inputs of the logic elements 9 when the current virtual address in register 15 is greater than or equal to the boundary value in register 14 and is not found in block 6. Block 12 sets a new value for the virtual and corresponding real address in block b.
    The operation of the device is explained in more detail using FIG. 2 and 3.
    Steps 20-22 (see FIG. 2) represent the operation of the device described above. The virtual address that comes from block 1 is compared with the value stored in register 14. If the virtual address is less than the boundary address, then block 2 is selected by the virtual address. If the virtual address is greater than or limited to the boundary address, then the virtual address is used as a search argument in block 6. The associative matrix of block 6 is probed to determine whether the matrix contains a virtual address and its corresponding real address. If the virtual address is in the associative matrix, then its real address is used to select block 2. If the virtual address is not in the associative matrix, then control is passed to step 23.
    In steps 23, 24, block 1 transfers tables 7 and from 8-1 to 8-N to block 2, for example, using firmware to determine the location of the desired real address in the tables. If the corresponding page is in block 2, then the corresponding real address will be found in one of the tables from 8-1 to 8-N. The actual battle of the page table is used to determine whether the virtual page is valid or not, that is, whether it is in block 2 and ’is available for selection.
    If the page is not valid, then control is passed to step 25.
    In the proposed device, each virtual address includes a segment part represented by the most significant bits of the address, a page part represented by intermediate bits, and a dictionary or bit part represented by the least significant bits. The segment part of the virtual address along with the segment table of the start pointer (stored in a register that is not shown in Figs. 1-3) selects the required input in table 7. The page part of the virtual address and read input of table 7 during the search in steps 23 -24 is used to select the required input 1 in the selected table from 8-1 to 8-N. The selected tabular data in one of the tables from 8-1 to 8-N has the vocabulary part of the virtual address associated, moreover, with the corresponding real address.
    If the page is valid, then control is transferred to the э stage ’GB, in which the virtual address and the real address are set in block b to control the least recently used address (using block 12). Block 2 can now be selected by transmitting 4 signals from block 6.
    The transfer of control to step 25 is determined by the equipment that provides the storage of the virtual address in a previously defined location in the cells of block 2. Next, block 1 selects a new directory address from another previously defined zone and starts a new directory action in step 27.
    At step 27, the page in block 2 is selected for recovery. Control is then transferred to steps 28 and 29, where the table directive is used to clear (reset all bit positions to zero) block 6 in order to agree on the cancellation of the page that was replaced.
    Subsequent step 29 or mutually exclusive subsequent stage device 30 The representation is measured (nenie contents of the register 14. This process may either restore a previously defined value or scan page tables.
    Signaling 1 and 0 “., Required. the allowable entry for the required page is performed in step 31 and the real address is stored on the corresponding input of the page table and made valid in step 30.
    The directory address stored in step 25 is reloaded into block 2 using the boot instruction, and the process returns to step 20.
    Steps 32, 33 (see, Fig. 3) are a firmware loop that starts at a virtual address of zero in the page tables and sets the real address to the virtual address, i.e. , the real address is read and compared with the virtual address to verify equality. If the virtual address is equal to the real address, then the virtual address is an increment of page size and the circuit again compares the next virtual page address entry table with the real address stored in the tabular data. This is repeated until the virtual address becomes equal to the set real address or until the register overflow 15.
    1 At step 34, the largest virtual address value that appears in steps 32 and 33 is entered into register 4 as the boundary address in block 2.
    In a typical device, the steps represented by positions 27, 28, 31, 30 and 35 (and possibly 36) are performed by the directive routine method.
    In the described device, in contrast to the known device, not all virtual addresses are converted. Certain virtual addresses are used to access the block of RAM directly, without conversion. The addresses indicated correspond to frequently accessed memory locations. Accessing such cells takes less time, as address translation is not required. Thus, it is possible to obtain a general increase in performance equal to 15-25%.
    权利要求:
    Claims (2)
    [1]
    page processing / fig. 3 illustrates an alternative method for setting a value that can be entered into a boundary register. A device for selecting an address (see FIG. 1) comprises a logic unit 1 serving for processing data; memory unit 2, memory unit on magnetic disks 3, first address register, 4, which serves to store the real address and has output 5, associative memory unit 6. Operative pack. Ti 2 contains zones 7, 8 called the segment table (7) and page tables (8-1 - 8-N). The device also contains the first 9, second 10 and third 11 groups of logical elements, the address setting unit 12, the comparison circuit 13, the information register 14, the second address register 15, which serves to store the virtual address. Blo: RAM 2 also contains nuclear zone 16. Inputs 17 and 18 of the comparison circuit 13 are connected to the outputs of the second address register 15 and information register 14, and one of the outputs to One of the inputs of logic elements DO and 11. One of the inputs of logical elements 9 are connected to the first output 19 of block 6. The other inputs of the logic elements 9-11 are connected CO correspondingly to the other output of the comparison circuit 13, the output of the second address register 15 and the second output of the block 6. The output of the logic elements 10 and 11 are connected to the input of the first address relays istra 4. The apparatus operates as follows. When it is required to select a cell and block 2 (see Fig. 1), then block 1 transfers the virtual address to the circuit of circuit 13 and block b through the register 15. PefMCTp 14 stores the value equal to the higher bits (the size of the boundary address page in block 2, below which the real addresses are virtual and equal to them. For example, the page is two thousand h bits, the lower twelve bits of the country addresses are not stored in the Setment table 7 and page tables 8-1 through 8-H are located in block 2. Table 7 has an input for each of the C virtual memory segments in block 3. Each entry has the following address: The initiator starts a page from 8-1 to 8-W. Each page table has a number of entries for the pages of the corresponding segment, which can be called in block 2 from block 3. Each input is valid Page 1 page 1Y contains a pointer to the beginning of page1 in block 2. The signal from one of the srnp; 7g1I1 13 s-G1x- | D) iruots .pig-iChcIs: .h ;; oggptlm1 GO-ut.ll, To set the virtual address to register 4, when the high-order bits of the virtual address supplied from block 1, less than the value stored 1G1a s in register 14. The same signal also comes in as a inhibitory signal to logic elements 11 in order to prevent the transfer of any real address from block b to register 4 when no conversion is required. The signals from logic elements 9 are needed in order to search for tables 7 and from 8-1 to 8-N, when signals are applied to the inputs of these elements. Signals are fed to the inputs of logic elements 9 when the current virtual address in register 15 is greater than or equal to the limit value in register 14 and is not found in block 6. Block 12 sets the new value of virtual and corresponding address addresses in block b. The operation of the device is explained in more detail with reference to FIG. 2 and 3, Steps 20-22 (see Fig. 2) represent the operation of the device described above. The virtual address that comes from block 1 is compared with the value stored in register 14. If the virtual address is less than the boundary address, then block 2 is selected by the virtual address. If the virtual address is greater than or the boundary address, then the virtual address is used as the search argument in block b. The associative matrix of the block b is probed to determine if the matrix contains a virtual address and a corresponding real address. If the virtual address is in the associative matrix, then its real address is used to select block 2. If the virtual address is not in the associative matrix, then control is transferred to step 23. In steps 23, 24, block 1 transmits tables 7 and from 8-1 to 8 N in block 2, for example, using a firmware in order to determine the location of the required real address in the tables. If the corresponding page is in block 2, then the corresponding real address will be found in one of the tables from 8-1 to 8-N. The actual bit in the paging table is used to determine if the virtual page is valid or not, i.e., it is in block 2 and available for selection. If the page is not valid, then the control is transferred to step 25. In the proposed device, each virtual address includes a segment part represented by the most significant address bits, a page part, provided K1 t1r) inter-word-reading 7 bits, and dictionaries and bit part represented by lower order bits. The segment part of the virtual address, together with the segment start table (the register is stored, which is not shown in Fig. 1-3) selects the required entry in Table 7. The page part of the virtual page and the read input of Table 7 during the search time in steps 23- 24 is used to sample the desired input in the selected table from 8-1 to 8-M. The selected table data in one of the tables from 8-1 to 8-N have the dictionary part of the virtual address associated, moreover, with the corresponding real address. If the page is valid, control is transferred to step 26, where the virtual address and real address is set in block b to control the least recently used address (using block 12). Block 2 now the mohset will be selected by transmitting the signals of block 6. The transfer of control to step 25 is determined by the equipment that stores the virtual address in a previously defined place in the cells of block 2 Next, block 1 selects a new directive address from another previously defined zone the policy action in step 27. At step 27, the page in block 2 is selected for recovery. The control transfer is then carried out at this point 28 and 29, where the table directive is used to clear (reset all bit positions to zero) block b in order to reconcile annotation of the page that has been replaced. The subsequent step 29 or the mutually exclusive next step 30 of the presented device causes the contents of the register 14 to change. This process can either restore the previously determined value or scan the page tables. 31 and the real address is remembered at the corresponding entry of the page table and is made valid at step 30. The directory address remembered at step 25 is reloaded into block 2 from the load instruction and the process Returns to step 20. Steps 32, 33 (see FIG. 3) are a g / 1 software circuit that starts at zero virtual address in the page tables and sets the real address to the virtual address, i.e. the real address is read and compared with a virtual address to verify 5.1 validity. If the virtual ACPGC pnric 1) is ay, a; i; pecy, then virtualias: (page size is paged and the cF contour compares the following virtual page address entry table with the real address stored in the tabular data. This is repeated until as long as the virtual address becomes equal to the set real address or until the register 15 overflows. At step 34, the largest value of the virtual address itself, according to steps 32 and 33, enters register 4 as the boundary address in block 2. In a typical device The poses represented by the positions 27, 28, .31, 30, and 35 (and possibly 36) are performed by the method of subroutines.In the described device, in contrast to the known device, not all virtual addresses are converted. to the RAM directly, without conversion. These addresses correspond to memory cells that are often accessed. Addressing such cells takes less time, since address translation is not required. Thus, it is possible to obtain a general increase in speed equal to 15-25%. the memory, the first group of logic elements, one of the inputs of which are connected to the First output of the associative memory block, and the outputs to the input of the logical block connected to the second address register and to the operational block memory, that is, so that, in order to increase the speed of the device, it consists of the second and third groups logically; elements, information (Ny register and comparison circuit, which are connected to the outputs of the second address register and information register. And outputs - to one of the inputs of logical elements of the second and third groups, the outputs of which are connected to the input of the first address register, other inputs of logical elements connected, respectively, to the outputs cxeMij of the comparison, the second address register and the second output of the associative memory unit. Sources of information taken into account in the examination 1.US Patent No. 3412382, class 340-172.5, published in 1968.
    [2]
    2. Patent SHL No. 353307S, cl. 340-172.5, op. | L1 v. 1.470 (prototype).
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    JPS5171648A|1974-12-18|1976-06-21|Panafacom Ltd|
    JPS5275931A|1975-12-22|1977-06-25|Oki Electric Ind Co Ltd|Memory address extension mechanism for information processing unit|
    JPS5821305B2|1976-05-31|1983-04-28|Yokogawa Electric Works Ltd|
    JPS5821307B2|1976-09-14|1983-04-28|Yokogawa Electric Works Ltd|
    JPS5821306B2|1976-09-14|1983-04-28|Yokogawa Electric Works Ltd|
    JPS5435638A|1977-08-25|1979-03-15|Toshiba Corp|Address converter|
    JPS5435637A|1977-08-25|1979-03-15|Toshiba Corp|Address conversion system|
    DE2842288A1|1978-09-28|1980-04-17|Siemens Ag|DATA TRANSFER SWITCH WITH ASSOCIATIVE ADDRESS SELECTION IN A VIRTUAL MEMORY|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    US27404072A| true| 1972-07-21|1972-07-21|
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